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ML145053
10-Bit A/D Converter With Serial Interface
CMOS
Legacy Device: Motorola MC145053
This ratiometric 10-bit ADC has a serial interface port to provide communication with MCUs and MPUs. Either a 10- or 16-bit format can be used. The16-bit format can be one continuous 16-bit stream or two intermittent 8bit streams. The converter operates from a single power supply with no external trimming required. Reference voltages down to 4.0 V are accommodated. The ML145053 has an internal clock oscillator to operate the dynamic A/D conversion sequence and an end-of-conversion (EOC) output. * * * * * * * * * * * 5 Analog Input Channels with Internal Sample-and-Hold Operating Temperature Range: TA - 40 to 125C Successive Approximation Conversion Time: 44 s Maximum Maximum Sample Rate: 20.4 ks/s Analog Input Range with 5-Volt Supply: 0 to 5 V Monotonic with No Missing Codes Direct Interface to Motorola SPI and National MICROWIRETM Serial DataPorts Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible Low Power Consumption: 14 mW Chip Complexity: 1630 Elements (FETs, Capacitors, etc.) See Application Note AN1062 for Operation with QSPI
BLOCK DIAGRAM
Vref MUX OUT VAG P DIP 14 = CP PLASTIC CASE 646
SOG 14 = -5P SOG CASE 751A
CROSS REFERENCE/ORDERING INFORMATION MOTOROLA PACKAGE LANSDALE P DIP 14 MC145053P ML145053CP SOG 14 MC145053D ML145053-5P
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
PIN ASSIGNMENT
EOC AN0 AN1 AN2 AN3 AN4 VSS 1 2 3 4 5 6 7 14 VDD 13 SCLK 12 Din 11 Dout 10 CS 9 Vref 8 VAG
9 8 10-BIT RC DAC WITH SAMPLE AND HOLD
INTERNAL TEST VOLTAGES
2 AN0 3 AN1 ANALOG 4 MUX AN2 5 AN3 6 AN4 AN5 AN6 AN7 Din 12 Dout 11 CS SCLK EOC 10 13 1
SUCCESSIVE APPROXIMATION REGISTER MUX ADDRESS REGISTER
PIN 14 = VDD PIN 7 = VSS
DATA REGISTER AUTO-ZEROED COMPARATOR DIGITAL CONTROL LOGIC
MICROWIRE is a trademark of National Semiconductor Corp.
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MAXIMUM RATINGS*
Symbol VDD Vref VAG Vin Vout Iin Iout IDD, ISS Tstg TL Parameter DC Supply Voltage (Referenced to VSS) DC Reference Voltage Analog Ground DC Input Voltage, Any Analog or Digital Input DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VDD and VSS Pins Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds Value - 0.5 to + 6.0 VAG to VDD + 0.1 VSS - 0.1 to Vref VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDD + 0.5 20 25 50 - 65 to 150 260 Unit V V V V V mA mA mA C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Symbol VDD Vref VAG VAI Vin, Vout TA Parameter DC Supply Voltage, Referenced to VSS DC Reference Voltage Analog Ground Analog Input Voltage (See Note) Digital Input Voltage, Output Voltage Ambient Operating Temperature Value 4.5 to 5.5 VAG + 4.0 to VDD + 0.1 VSS - 0.1 to Vref - 4.0 VAG to Vref VSS to VDD - 40 to 125 Unit V V V V V C
NOTE: Analog input voltages greater than Vref convert to full scale. Input voltages less than VAG convert to zero. See Vref and VAG pin descriptions.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated) Symbol VIH VIL VOH VOL Iin IOZ IDD Iref IAl Parameter Minimum High-Level Input Voltage (Din, SCLK, CS) Maximum Low-Level Input Voltage (Din, SCLK, CS) Minimum High-Level Output Voltage (Dout, EOC) Minimum Low-Level Output Voltage (Dout, EOC) Maximum Input Leakage Current (Din, SCLK, CS) Maximum Three-State Leakage Current (Dout) Maximum Power Supply Current Maximum Static Analog Reference Current (Vref) Maximum Analog Mux Input Leakage Current between all deselected inputs and any selected input (AN0-AN4) Iout = - 1.6 mA Iout = - 20 A Iout = + 1.6 mA Iout = + 20 A Vin = VSS or VDD Vout = VSS or VDD Vin = VSS or VDD, All Outputs Open Vref = VDD, VAG = VSS VAl = VSS to VDD Test Condition Guaranteed Limit 2.0 0.8 2.4 VDD - 0.1 0.4 0.1 2.5 10 2.5 100 1 Unit V V V V A A mA A A
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A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table) Characteristic Resolution Maximum Nonlinearity Maximum Zero Error Maximum Full-Scale Error Maximum Total Unadjusted Error Maximum Quantization Error Absolute Accuracy Maximum Conversion Time Data Transfer Time Sample Acquisition Time Minimum Total Cycle Time Maximum Sample Rate Definition and Test Conditions Number of bits resolved by the A/D converter Maximum difference between an ideal and an actual ADC transfer function Difference between the maximum input voltage of an ideal and an actual ADC for zero output code Difference between the minimum input voltage of an ideal and an actual ADC for full-scale output code Maximum sum of nonlinearity, zero error, and full-scale error Uncertainty due to converter resolution Difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included Total time to perform a single analog-to-digital conversion Total time to transfer digital serial data into and out of the device Analog input acquisition time window Total time to transfer serial data, sample the analog input, and perform the conversion; SCLK = 2.1 MHz Rate at which analog inputs may be sampled; SCLK = 2.1 MHz Guaranteed Limit 10 1 1 1 1 1/2 1-1/2 44 10 to 16 6 49 20.4 Unit Bits LSB LSB LSB LSB LSB LSB s SCLK cycles SCLK cycles s ks/s
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AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table) Figure 1 Symbol f Clock Frequency, SCLK Note: Refer to twH, twL below 1 1 1, 7 1, 7 2, 7 2, 7 3 3 4, 7, 8 5 - - 5 6, 8 1 1, 4, 6 - 8 - - twH twL tPLH, tPHL th tPLZ, tPHZ tPZL, tPZH tsu th td tsu tCSd tCAs th tPHL tr, tf tTLH, tTHL Cin Cout Minimum Clock High Time, SCLK Minimum Clock Low Time, SCLK Maximum Propagation Delay, SCLK to Dout Minimum Hold Time, SCLK to Dout Maximum Propagation Delay, CS to Dout High-Z Maximum Propagation Delay, CS to Dout Driven Minimum Setup Time, Din to SCLK Minimum Hold Time, SCLK to Din Maximum Delay Time, EOC to Dout (MSB) Minimum Setup Time, CS to SCLK Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and CS to Allow a Conversion Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to Abort a Conversion Minimum Hold Time, Last SCLK to CS Maximum Propagation Delay, 10th SCLK to EOC Maximum Input Rise and Fall Times Maximum Output Transition Time, Any Output Maximum Input Capacitance Maximum Three-State Output Capacitance AN0 - AN4 SCLK, CS, Din Dout SCLK Din, CS Parameter (10-bit xfer) Min (11- to 16-bit xfer) Min (10- to 16-bit xfer) Max) Guaranteed Limit 0 Note 1 2.1 190 190 125 10 150 2.3 100 0 100 2.425 Note 2 9 0 2.35 1 10 300 55 15 15 s ns s ms s ns pF pF Unit MHz
ns ns ns ns ns s ns ns ns s
NOTES: 1. After the 10th SCLK falling edge ( 2 V), at least 1 SCLK rising edge ( 2 V) must occur within 18.5 s. 2. A CS edge may be received immediately after an active transition on the EOC pin.
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SWITCHING WAVEFORMS
tWL tf 2.0 V SCLK 0.8 V 1/f tPLH, tPHL 2.4 V Dout 0.4 V tTLH, tTHL Dout 2.4 V 0.4 V tWH tr 2.0 V 0.8 V tPZH, tPZL tPHZ, tPLZ 90% 10%
CS
Figure 1.
Figure 2.
tTLH 2.4 V VALID Din 2.0 V 0.8 V th tsu SCLK 2.0 V 0.8 V Dout EOC 0.4 V td 2.4 V 0.4 V VALID MSB
NOTE: D out is driven only when CS is active (low).
Figure 3.
Figure 4.
2.0 V CS 0.8 V tsu FIRST CLOCK LAST CLOCK th
SCLK
10TH CLOCK
0.8 V tPHL
EOC 0.8 V
2.4 V 0.4 V tTHL
SCLK
0.8 V
Figure 5.
Figure 6.
VDD TEST POINT Dout DEVICE UNDER TEST EOC TEST POINT
VDD
12 k
100 pF
DEVICE UNDER TEST
12 k
50 pF
Figure 7. Test Circuit
Figure 8. Test Circuit
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ML145053
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS DIGITAL INPUTS AND OUTPUT The various serial bit-stream formats for the ML145053 are illustrated in the timing diagrams of Figures 9 through 14. Table 1 assists in selection of the appropriate diagram. Note that the ADC accepts 16 clocks which makes it SPI (Serial Peripheral Interface) compatible.
Table 1. Timing Diagram Selection
No. of Clocks in Serial Transfer 10 10 11 to 16 16 11 to 16 16 Using CS Yes No Yes No Yes No Serial Transfer Interval Don't Care Don't Care Shorter than Conversion Shorter than Conversion Longer than Conversion Longer than Conversion Figure No. 9 10 11 12 13 14
CS Active-Low Chip Select Input (Pin 10) Chip select initializes the chip to perform conversions and provides 3-state control of the data output pin (Dout). While inactive high, CS forces Dout to the high-impedance state and disables the data input (Din) and serial clock (SCLK) pins. A high-to-low transition on CS resets the serial dataport and synchronizes it to the MPU data stream. CS can remain active during the conversion cycle and can stay in the active low state for multiple serial transfers or CS can be inactive high after each transfer. If CS is kept active low between transfers, the length of each transfer is limited to either 10 or 16 SCLK cycles. If CS is in the inactive high state between transfers, each transfer can be anywhere from 10 to16 SCLK cycles long. See the SCLK pin description for a more detailed discussion of these requirements. Spurious chip selects caused by system noise are minimized by the internal circuitry. Any transitions on the CS pin are recognized as valid only if the level is maintained for about 2 s after the transition. NOTE If CS is inactive high after the 10th SCLK cycle and then goes active low before the A/D conversion is complete, the conversion is aborted and the chip enters the initial state, ready for another serial transfer/conversion sequence. At this point, the output data register contains the result from the conversion before the aborted conversion. Note that the last step of the A/D conversion sequence is to update the output data register with the result. Therefore, if CS goes active low in an attempt to abort the conversion too close to the end of the conversion sequence, the result register may be corrupted and the chip could be thrown out of sync with the processor until CS is toggled again (refer to the AC Electrical Characteristics in the spec tables).
Dout Serial Data Output of the A/D Conversion Result (Pin 11) This output is in the high-impedance state when CS is inactive high. When the chip recognizes a valid active low on CS, Dout is taken out of the high-impedance state and is driven with the MSB of the previous conversion result. (For the first transfer after power-up, data on Dout is undefined for the entire transfer.) The value on Dout changes to the second most significant result bit upon the first falling edge of SCLK.The remaining result bits are shifted out in order, with the LSB appearing on Dout upon the ninth falling edge of SCLK. Note that the order of the transfer is MSB to LSB. Upon the10th falling edge of SCLK, Dout is immediately driven low (if allowed by CS) so that transfers of more than 10 SCLKs read zeroes as the unused LSBs. When CS is held active low between transfers, Dout is driven from a low level to the MSB of the conversion result for three cases: Case 1 - upon the 16th SCLK falling edge if the transfer is longer than the conversion time (Figure 14); Case 2 - upon completion of a conversion for a 16-bit transfer interval shorter than the conversion (Figure 12); Case 3 - upon completion of a conversion for a 10-bit transfer (Figure 10). Din Serial Data Input (Pin 12) The four-bit serial input stream begins with the MSB of the analog mux address (or the user test mode) that is to be converted next. The address is shifted in on the first four rising edges of SCLK. After the four mux address bits have been received, the data on Din is ignored for the remainder of the present serial transfer. See Table 2 in Applications Information. SCLK Serial Data Clock (Pin 13) This clock input drives the internal I/O state machine to perform three major functions: (1) drives the data shift registers to simultaneously shift in the next mux address from the Din pin and shift out the previous conversion result on the Dout pin, (2) begins sampling the analog voltage onto the RCDAC as soon as the new mux address is available, and (3) transfers control to the A/D conversion state machine after the last bit of the previous conversion result has been shifted out on the Dout pin. The serial data shift registers are completely static, allowing SCLK rates down to the DC. There are some cases, however, that require a minimum SCLK frequency as discussed later in this section. At least ten SCLK cycles are required for each simultaneous data transfer. If the 16-bit format is used, SCLK can be one continuous 16-bit stream or two intermittent 8-bit streams. After the serial port has been initiated to perform a serial transfer*, the new mux address is shifted in
*The serial port can be initiated in three ways: (1) a recognized CS falling edge, (2) the end of an A/D conversion if the port is performing either a 10-bit or a 16-bit "shorter-than-conversion" transfer with CS active low between transfers, and (3) the 16th falling edge of SCLK if the port is performing 16-bit "longer-than-conversion" transfers with CS active low between transfers.
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on the first four rising edges of SCLK, and the previous 10-bit conversion result is shifted out on the first nine falling edges of SCLK. After the fourth rising edge of SCLK, the new mux address is available; therefore, on the next edge of SCLK (the fourth falling edge), the analog input voltage on the selected mux input begins charging the RC DAC and continues to do so until the tenth falling edge of SCLK. After this tenth SCLK edge, the analog input voltage is disabled from the RC DAC and the RC DAC begins the "hold" portion of the A/D conversion sequence. Also upon this tenth SCLK edge, control of the internal circuitry is transferred to the internal clock oscillator which drives the successive approximation logic to complete the conversion. If 16 SCLK cycles are used during each transfer, then there is a constraint on the minimum SCLK frequency. Specifically, there must be at least one rising edge on SCLK before the A/D conversion is complete. If the SCLK frequency is too low and a rising edge does not occur during the conversion, the chip is thrown out of sync with the processor and CS needs to be toggled in order to restore proper operation. If 10 SCLKs are used per transfer, then there is no lower frequency limit on SCLK. Also note that if the ADC is operated such that CS is inactive high between transfers, then the number of SCLK cycles per transfer can be anything between 10 and 16 cycles, but the "rising edge" constraint is still in effect if more than 10 SCLKs are used. (If CS stays active low for multiple transfers, the number of SCLK cycles must be either 10 or 16.) EOC End-of-Conversion Output (Pin 1) EOC goes low on the tenth falling edge of SCLK. A low-tohigh transition on EOC occurs when the A/D conversion is complete and the data is ready for transfer. ANALOG INPUTS AND TEST MODES AN0 through AN4 Analog Multiplexer Inputs (Pins 2 - 6) The input AN0 is addressed by loading $0 into the mux address register. AN1 is addressed by $1, AN2 by $2, AN3 by $3, and AN4 by $4. Table 2 shows the input format for a 16-bit stream. The mux features a break-before-make switching structure to minimize noise injection into the analog inputs. The source resistance driving these inputs must be 1 k. During normal operation, leakage currents through the analog mux
from unselected channels to a selected channel and leakage currents through the ESD protection diodes on the selected channel occur. These leakage currents cause an offset voltage to appear across any series source resistance on the selected channel. Therefore, any source resistance greater than 1 k (Lansdale test condition) may induce errors in excess of guaranteed specifications.There are three tests available that verify the functionality of all the control logic as well as the successive approximation comparator. These tests are performed by addressing $B, $C, or $D and they convert a voltage of (Vref + VAG)/2, VAG, or Vref, respectively. The voltages are obtained internally by sampling Vref or VAG onto the appropriate elements of the RC DAC during the sample phase. Addressing $B, $C, or $D produces an output of $200 (half scale), $000, or $3FF (full scale), respectively, if the converter is functioning properly. However, deviation from these values occurs in the presence of sufficient system noise (external to the chip) onVDD, VSS, Vref, or VAG. POWER AND REFERENCE PINS VSS and VDD Device Supply Pins (Pins 7 and 14) VSS is normally connected to digital ground; VDD is connected to a positive digital supply voltage. Low frequency (VDD - VSS) variations over the range of 4.5 to 5.5 volts do not affect the A/D accuracy. (See the Operations Ranges Table for restrictions on Vref and VAG relative to VDD and VSS.) Excessive inductance in the VDD or VSS lines, as on automatic test equipment, may cause A/D offsets > 1 LSB. Use of a 0.1 F bypass capacitor across these pins is recommended. VAG and Vref Analog Reference Voltage Pins (Pins 8 and 9) Analog reference voltage pins which determine the lower and upper boundary of the A/D conversion. Analog input voltages Vref produce a full scale output and input voltages VAG produce an output of zero. CAUTION: The analog input voltage must be VSS and VDD. The A/D conversion result is ratiometric to Vref - VAG. Vref and VAG must be as noisefree as possible to avoid degradation of the A/D conversion. Ideally, Vref and VAG should be single-point connected to the voltage supply driving the system's transducers. Use of a 0.22 F bypass capacitor across these pins is strongly urged.
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CS
Dout
D9-MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
D9
1 SCLK
2
3
4
5
6
7
8
9
10
1
Din MSB EOC SHIFT IN NEW MUX ADDRESS, SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE INITIALIZE A/D CONVERSION INITERVAL
A3
RE-INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS
MUST BE HIGH ON POWER UP CS
Dout
D9-MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOW LEVEL
D9
1 SCLK
2
3
4
5
6
7
8
9
10
1
Din
A3 MSB
A2
A1
A0
A3
EOC A/D CONVERSION INITERVAL
INITIALIZE
SHIFT IN NEW MUX ADDRESS, SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTES: 1. D9, D8, D7, D6, D5, ..., D0 = the result of the previous A/D conversion. 2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
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D9-MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LOW LEVEL D9 HIGH IMPEDANCE 1 2 3 4 5 6 7 8 9 10 11 16 1 A3 A2 A1 A0 A3 SHIFT IN NEW MUX ADDRESS SIMUTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE A/D CONVERSION INTERVAL RE-INITIALIZE D7 D6 D5 D4 D3 D2 D1 D0 LOW LEVEL D9 2 SAMPLE ANALOG OUTPUT A1 A0 A3 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 A/D CONVERSION INTERVAL
CS
Dout
SCLK
Din
EOC
INITIALIZE
Figure 11. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
CS
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Dout
D9-MSB
D8
SCLK
1
Din
A3
A2
EOC
INITIALIZE
SHIFT IN NEW MUX ADDRESS SIMUTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
NOTES: D9, D8, D7, . . . , D0 = the result of the previous A/D conversion. A3, A2, A1, A0 = the mux address for the next A/D conversion.
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HIGH IMPEDANCE D9 D9-MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LOW LEVEL 1 SAMPLE ANALOG INPUT A3 A2 A1 A0 NOTE 2 A3 2 3 4 5 6 7 8 9 10 11 16 1 SHIFT IN NEW MUX ADDRESS SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE A/D CONVERSION INTERVAL RE-INITIALIZE
CS
Dout
SCLK
Din
EOC
INITIALIZE
Figure 13. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Longer Than Conversion)
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D7 D6 D5 D4 D3 D2 D1 D0 2 SAMPLE ANALOG INPUT 3 4 5 6 7 8 9 10 11 12 13 A/D CONVERSION INTERVAL
D9-MSB
D8
LOW LEVEL
D9
1
14 NOTE 2
15
16
1
A3
SHIFT IN NEW MUX ADDRESS SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
Figure 14. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Longer Than Conversion)
NOTES: D9, D8, D7, . . . , D0 = the result of the previous A/D conversion. A3, A2, A1, A0 = the mux address for the next A/D conversion. *NOTES: 1. The 11th SCLK rising edge must occur before the conversion is complete. Otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer.
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ML145053
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Legacy Applications Information
DESCRIPTION This example application of the ML145053 ADC interfaces four analog signals to a microprocessor. Figure 15 illustrates how the ML145053 is used as a cost effective means to simplify this type of circuit design. Utilizing one ADC, four analog inputs are interfaced to a CMOS or NMOS microprocessor with a serial peripheral interface (SPI) port. Processors with National Semiconductor's MICROWIRE serial port may also be used. Full duplex operation optimizes throughput for this system. DIGITAL DESIGN CONSIDERATIONS Motorola's MC68HC05C4 CMOS MCU may be chosen to reduce power supply size and cost. The NMOS MCUs may be used if power consumption is not critical. A VDD or VSS 0.1 F bypass capacitor should be closely mounted to the ADC. The ML145053 has the end-of-conversion (EOC) signal at output pin 1 to define when data is ready. ANALOG DESIGN CONSIDERATIONS Analog signal sources with output impedances of less than 1 k may be directly interfaced to the ADC, eliminating the need for buffer amplifiers. Separate lines connect the Vref and VAG pins on the ADC with the controllers to provide isolation from system noise. Although not indicated in Figure 15, the Vref and sensor output lines may need to be shielded, depending on their length and electrical environment. This should be verified during prototyping with an oscilloscope. If shielding is required, a twisted pair or foil-shielded wire (not coax) is appropriate for this low frequency application. One wire of the pair or the shield must be VAG. A reference circuit voltage of 5 volts is used for the application shown in Figure 15. However, the reference circuitry may be simplified by tying VAG to system ground and Vref to the system's positive supply. (See Figure 16.) A bypass capacitor of approximately 0.22 F across theVref and VAG pins is recommended. These pins are adjacent on the ADC package which facilitates mounting the capacitor very close to the ADC. SOFTWARE CONSIDERATIONS The software flow for acquisition is straight forward. The four analog inputs, AN0 through AN3, are scanned by reading the analog value of the previously addressed channel into the MCU and sending the address of the next channel to be read to the ADC, simultaneously. The designer utilizing the ML145053 has the end-of-conversion signal (at pin 1) to define the conversion interval. EOC may be used to generate an interrupt, which is serviced by reading the serial data from the ADC. The software flow should then process and format the data. When this ADC is used with a 16-bit (2-byte) transfer, there are two types of offsets involved. In the first type of offset, the channel information sent to the ADCs is offset by 12 bits. That is, in the 16-bit stream, only the first 4 bits (4 MSBs) contain the channel information. The balance of the bits are don't cares. This results in 3 don't-care nibbles, as shown in Table 2. The second type of offset is in the conversion result returned from the ADC; this is offset by 6 bits. In the 16-bitstream, the first 10 bits (10 MSBs) contain the conversion result. The last 6 bits are zeroes. The hexadecimal result is shown in the first column of Table 3. The second column shows the result after the offset is removed by a micro-processor routine. If the 16bit format is used, the ADC can transfer one continuous 16-bit stream or two intermittent 8-bitstreams.
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Legacy Applications Information
Table 2. Programmer 's Guide for 16-Bit Transfers: Input Code
Input Address in Hex $0XXX $1XXX $2XXX $3XXX $4XXX $5XXX $6XXX $7XXX $8XXX $9XXX $AXXX $BXXX $CXXX $DXXX $EXXX $FXXX Channel to be Converted Next AN0 AN1 AN2 AN3 AN4 None None None None None None AN5 AN6 AN7 None None
Table 3. Programmer 's Guide for 16-Bit Transfers: Output Code
Conversion Result Without Offset Removed $0000 $0040 $0080 $00C0 $0100 $0140 $0180 $01C0 $0200 $0240 $0280 $02C0 $FF40 $FF80 $FFC0 Conversion Result With Offset Removed $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $03FD $03FE $03FF
Comment Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Half Scale Test: Output = $8000 Zero Test: Output = $0000 Full Scale Test: Output = $FFC0 Not Allowed Not Allowed
Value Zero Zero + 1 LSB Zero + 2 LSBs Zero + 3 LSBs Zero + 4 LSBs Zero + 5 LSBs Zero + 6 LSBs Zero + 7 LSBs Zero + 8 LSBs Zero + 9 LSBs Zero + 10 LSBs Zero + 11 LSBs Full Scale - 2 LSBs Full Scale - 1 LSB Full Scale
+5V 0.1 F 0.22F Vref AN0 ANALOG SENSORS, ETC. AN1 AN2 AN3 EOC AN4 ML145053 ADC VDD CS Din SCLK Dout P SPI PORT
5 VOLT REFERENCE CIRCUIT
VAG
VSS
Figure 15. Example Application
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Legacy Applications Information
DIGIGAL + V ANALOG + V Vref VDD DO NOT CONNECT AT IC
5V SUPPLY
TO SENSORS, ETC.
0.22 F
ML145053
0.1 F
ANALOG GND DIGITAL GND
VAG
VSS DO NOT CONNECT AT IC
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola's MCUs/MPUs. Contact your Motorola representative if you need additional information. Instruction Set M6805 Memory (Bytes) ROM 2096 2096 4160 4160 8K 4160 8K 7700 - - EEPROM - - - - - - - - 4160 - SPI SCI - Ys e Ys e Ys e Ys e Ys e Ys e Ys e - - Motorla Part Number MC68HC05C2 MC68HC05C3 MC68HC05C4 MC68HSC05C4 MC68HSC05C8 MC68HCL05C4 MC68HCL05C8 MC68HC05C8 MC68HC805C4 MC68HC000
M68000
1 SPI = Serial Peripheral Interface. 2 SCI = Serial Communication Interface. 3 High Speed. 4 Low Power .
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OUTLINE DIMENSIONS
PLASTIC DIP (ML145053CP) CASE 646-06
14
8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL
INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0 10 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
DIM A B C D F G H J K L M N
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SOG PACKAGE (ML145053-5P) CASE 751A-03
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION 4. MAXIMUM HOLD PROTRUSION 0.15 (0.006) PER SIDE 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION
-A14 8
-B1 7
P7
PL
0.25 (0.010)
M
B
M
G C
R X 45
F
SEATING PLANE
K 0.25 (0.010)
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
INCHES MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50
MILLIMETERS MIN MAX 0.337 0.334 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue A

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